1. Field of the Invention
The present invention relates to a test circuit for semiconductor integrated circuit, and in particular to a scan test circuit that conducts a scan test on a semiconductor integrated circuit at its actual operation speed (at-speed scan test circuit).
2. Related Background Art
As means to detect failures or troubles in the chip manufacturing process for semiconductor integrated circuits, importance of at-speed test, in which a test for a semiconductor integrated circuit is conducted at the actual operation speed of the circuit, has increased. Especially, if the at-speed test can be executed in a scan test, in which the failure detection factor can be improved easily, failures or troubles in the chip manufacturing process can be detected with a considerable probability.
One of scan test circuits that are the most practical in implementing the at-speed scan test in the background art is a scan test circuit formed of two-phase clocked sequential circuits.
In the case of a scan test circuit formed of two-phase clocked sequential circuits, however, there is a problem. If data that is the same as data one cycle before is input from a sequential circuit to a combinational circuit included in a path to be subjected to scan test at the time of scan shift, i.e., at a rising edge of a scan clock pulse, the at-speed scan test can not be implemented.
In other words, the same data is input from the sequential circuit to the combinational circuit from one cycle earlier. Even if it is attempted to increase the speed of the clocked operation and analyze the signal propagation in the path to be analyzed at the actual operation speed, the path is judged to have apparently passed the test if an output having a proper value has arrived at an output node of the combinational circuit within a time corresponding to two cycles.
Therefore, the conventional scan test circuit formed of two-phase clocked sequential circuits has a problem that a correct test result sometimes cannot be obtained.
Another scan test circuit having a possibility that the at-speed scan test can be implemented in the background art is a scan test circuit formed of one-phase clocked sequential circuits.
FIG. 1 is a block diagram of a conventional scan test circuit formed of one-phase clocked sequential circuits. In FIG. 1, only components of three lines each including a combinational circuit of one stage are shown.
The conventional scan test circuit formed of one-phase clocked sequential circuits includes cascade-connected first sequential circuit S1, first combinational circuit C1 and second sequential circuit S2, cascade-connected third sequential circuit S3, second combinational circuit C2 and fourth sequential circuit S4, and cascade-connected fifth sequential circuit S5, third combinational circuit C3 and sixth sequential circuit S6.
A scan input TI of the third sequential circuit S3 disposed at the top of the second line is supplied with an output Q or an inverted output QN of the first sequential circuit S1 disposed at the top of the first line. A scan input TI of the fifth sequential circuit S5 disposed at the top of the third line is supplied with an output Q or an inverted output QN of the third sequential circuit S3 disposed at the top of the second line.
In FIG. 1, the case where the scan inputs TI of the third sequential circuit S3 and the fifth sequential circuit S5 are supplied respectively with the inverted outputs QN of the first sequential circuit S1 and the third sequential circuit S3 is shown as an example.
Furthermore, in the example shown in FIG. 1, the output Q of the third sequential circuit S3 is input to the first combinational circuit C1. An output Q of the fifth sequential circuit S5 is input to the second combinational circuit C2.
FIG. 2 is a timing chart of the scan clock in the conventional scan test circuit formed of one-phase clocked sequential circuits.
In a scan test in the above-described conventional scan test circuit, shift data supplied from a shift data input/output port I/O are set in the first sequential circuit S1, the third sequential circuit S3 and the fifth sequential circuit S5 at scan shift timing, which is a rising edge of the scan clock, and scan data corresponding to the shift data are input from the first sequential circuit S1, the third sequential circuit S3 and the fifth sequential circuit S5 to the first combinational circuit C1, the second combinational circuit C2 and the third combinational circuit C3, respectively.
Output data that are consequently output from the first combinational circuit C1, the second combinational circuit C2 and the third combinational circuit C3 are captured by a second sequential circuit S2, a fourth sequential circuit S4 and a sixth sequential circuit S6 at a rising edge of the scan clock in a subsequent repetition period. As a result, operations of the first combinational circuit C1, the second combinational circuit C2 and the third combinational circuit C3 are evaluated.
As heretofore described, several scan test circuits formed of one-phase clocked sequential circuits have been proposed. An example thereof is described in, for example, Japanese Patent Laid-Open Publication No. 2002-289776.
In the case where a scan test circuit is formed of one-phase clocked sequential circuits, however, a scan mode of a system clock is used as the scan clock supplied to the sequential circuits at the time of the scan test. Therefore, repetition periods of the scan clock, i.e., periods A, B and C shown in FIG. 2 are always fixed (to for example, 30 ns).
In order to implement the at-speed scan test, therefore, there is no other way than making the scan clock frequency higher.
Even if the scan clock frequency is made high, however, it is also necessary to set the shift data from the shift data input/output port I/O at high speed in order to implement the at-speed scan test.
Among testers used in the scan test to set the shift data, however, a tester having an operation clock frequency that is as high as the clock frequency in the actual operation speed of semiconductor integrated circuits to be tested is very expensive.
Heretofore, therefore, practical use of the at-speed scan test circuits has been considered to be difficult.